The memory cells of a semiconductor memory component in each case have a transistor structure having a channel region in semiconductor material between source and drain, a gate electrode electrically insulated from the channel region, and associated electrical terminals. In a memory cell array with NOR architecture, for example, the gate electrodes are connected to one another row-wise via word lines and the drain regions are connected to one another column-wise via bit lines. For the programming of a memory cell, a memory layer is situated between the gate electrode and the channel, which memory layer is electrically insulated both from the gate electrode and from the semiconductor material of the channel region and may be a floating gate electrode, for example. A floating gate electrode is formed by an electrical conductor that is electrically insulated all around and is not connected to any potential. Charge carriers, preferably electrons, may be accumulated on the floating gate electrode and define the programming state.
Depending on the cell conception, the electrons pass for example by Fowler-Nordheim tunneling through the electrically insulating material between the channel region and the floating gate electrode or by injection of hot electrons from the channel (CHE, channel hot electrons) onto the floating gate electrode. In the case of the last-mentioned programming operation, electrons are accelerated in the channel region and pass as hot, i.e., high-energy, electrons via the lower insulation layer (gate oxide) into the memory layer. In the case of such memory cells, the erase operation is effected by Fowler-Nordheim tunneling of charge carriers through one of the insulation layers bounding the memory layer.
Instead of a memory layer made of conductive material, electrically insulating material may also be provided, as in the case of so-called charge trapping memory cells, in which the memory layer is, for example, a nitride layer between oxide layers. During the programming operation, electrons are accelerated in the channel region and pass as hot, i.e., high-energy, electrons through the lower oxide layer into the memory layer made of nitride. During the erase operation, Fowler-Nordheim tunneling of charge carriers through one of the oxide layers is effected in the case of such memory cells, too.
The further explanations relate specifically to the case of a flash cell with a floating gate electrode. A potential of 0 volts (ground) is in each case assumed as basic potentials for the word lines and the bit lines. During an erase operation of a memory cell row, a positive voltage is applied to the relevant word line, which voltage draws electrons onto the floating gate. During a programming operation by which a bit is written to the memory cell (write), a negative electrical potential is applied to the associated word line. The bit line of the column of the relevant memory cell is connected to a positive potential, while the nonselected columns have a bit line voltage of 0 volts. The negative electrical potential on the word line is present at all the gate electrodes of the memory cells of the relevant row. As a result, a so-called gate disturb occurs at all the nonselected memory cells and, in the case of the predominant number of memory cells, leaves the information stored therein unchanged.
However, there are a certain number of memory cells, which exhibit a significant shift in the threshold voltage after a gate disturb, so that the relevant cell is practically reprogrammed. Consequently, the relevant cell fails as an information carrier or must at least be programmed anew. These sporadically and randomly distributed incorrect programmings of the information content are referred to as erratic bits. Each memory cell may have such an incorrect behavior with a certain probability in each programming cycle. However, the entire memory is already incorrectly programmed if just a single bit has been incorrectly programmed. Therefore, an incorrect programming of the entire memory may occur with a relatively high probability in each programming cycle. However, the erratic bits do not have the effect that the memory as such is defective; the memory cells with erratic bits may already have a normal behavior again in the next cycle.
In principle, any cell may be affected by the occurrence of erratic bits. As a result, incorrect programmings may occur repeatedly in the application of the memory component. The problem cannot be eliminated by selection of functional components. Hitherto, the cells have been correctly programmed, as necessary, by repeated erase-write cycles. If appropriate, the error rate of the memory chip is reduced by means of an ECC (error correction code) at least to an extent such that specified product requirements are complied with. It would be desirable, however, to have a flash memory chip in which the occurrence of erratic bits is at least largely avoided.